1. Field of the Invention
This invention relates generally to improvements in timing distribution and specifically to a system and method for flexibly distributing timing signals between an application specific integrated circuit (ASIC) or a microprocessor and a memory device.
2. Description of the Background Art
Integrated circuits often exchange timing signals among themselves in order to synchronize data and other signal transfers. A common example of these timing signals is a clock signal, often used to synchronize the transfer of data between an ASIC or a processor and a memory device. Clock signals allow the transfer of data after numerous parallel data lines reach a stable logical state, thus eliminating data corruption.
In order for clock signals to accurately synchronize the data transfers, the clock signals must arrive at destination points in the circuit in the correct time sequence. It may be difficult to ensure the arrival of the clock signals in the correct time sequence when the clock signals originate at or near a single point on the die of the processor or ASIC. Clock signals may be delayed due to varying distances of propagation, and also due to parasitic impedances in the integrated circuit""s die, pads, bond wires, leads, and the printed circuit board""s traces. This situation in which the clock signals arrive at varying points at different times is referred to as clock skew.
Referring now to FIG. 1, a block diagram for a direct attachment of an application specific integrated circuit (ASIC) 10 to a synchronous dynamic random access memory (SDRAM) 70 is shown. In the FIG. 1 embodiment, ASIC 10 is chosen as an exemplary circuit, but may be a microprocessor or other electronic circuit in alternate embodiments. Similarly, in the FIG. 1 embodiment SDRAM 70 is shown, but in alternate embodiments SDRAM 70 may be any other type of memory device or any other type of integrated circuit requiring an external clock signal.
ASIC 10 includes a localized area 12 where the data input flip-flops 14, data output flip-flops 60, and address output flip-flops 16 are located. Data input flip-flops 14, data output flip-flops 60, and address output flip-flops 16 may latch a large number of signals, but for clarity the exemplary FIG. 1 example shows only two signals each. Data input flip-flops 14 connect via buffers 66, 68, to data lines 22, 30. Data output flip-flops 60 connect via tri-state buffers 62, 64, to data lines 22, 30. Data input flip-flops 14, data output flip-flops 60, and address output flip-flops 16 are clocked by a clock signal generated by clock generator 18 and distributed on clock signal line 20. The clock signal generated by clock generator 18 also clocks SDRAM 70 via a path that includes clock signal line 20, pad, bond-wire, and lead 54, printed circuit board (PCB) trace 56, and pad, bond-wire, and lead 58. Due to the additional path length and impedance, the clock signal will arrive at SDRAM 70 at some time subsequent to the clock signal""s arrival at data input flip-flops 14 and address output flip-flops 16. The foregoing is an example of clock skew.
Address signals generated by address output flip-flops 16 travel to SDRAM 70 along paths of varying length and impedance. One address signal travels via a path including address line 38, pad, bond-wire, and lead 40, printed circuit board (PCB) trace 42, and pad, bond-wire, and lead 44. Another address signal travels via a path including address line 46, pad, bond-wire, and lead 48, printed circuit board (PCB) trace 50, and pad, bond-wire, and lead 52. Because address output flip-flops 16 are within localized area 12, and because the pads, bond-wires, and leads 40 and 48 are distributed around the periphery of the die and package of ASIC 10, the address signals have differing propagation delays leaving ASIC 10. Additionally, PCB traces 42 and 50, and the pads, bond-wires, and leads 44 and 52 of SDRAM 70 may also possess differing lengths and configurations. For all of these reasons, the address signals may have very different propagation delays and times of arrival in SDRAM 70.
A similar situation occurs with the data signals arriving at data input flip-flops 14 from SDRAM 70. One data signal arrives at data input flip-flops 14 via pad, bond-wire, and lead 28, PCB trace 26, pad, bond-wire, and lead 24, data line 22, and buffer 66. Another data signal arrives at data input flip-flops 14 via pad, bond-wire, and lead 36, PCB trace 34, pad, bond-wire, and lead 32, data line 30, and buffer 68. For reasons analogous to those stated above in the discussion of the address signals, the data signals may have very different propagation delays and times of arrival in data flip-flops 14.
The foregoing differences in the propagation delays of the address, data, and clock signals may combine to cause errors in data transfer synchronization. For example, if the address flip-flops in SDRAM 70 are clocked before the address signals have stable values, an erroneous address may be input into SDRAM 70. Similarly, if the data flip-flops 14 are clocked before the data signals have stable values, erroneous data may be input into data flip-flops 14 of ASIC 10. Timing is therefore a significant consideration in the design of electronic circuits.
The present invention includes a system and method for flexibly distributing timing signals. Separate programmable clock generators generate and distribute clock signals which vary in delay with respect to one another. The programmable clock generators may be designed and fabricated prior to determining the relative delays needed in a particular application. The relative delays needed may then be programmed into the circuits after fabrication. Allowing the programming of the delays after the circuits are fabricated may allow for shorter development cycles.
In one embodiment of the present invention, five programmable clock generators (CG) CG1, CG2, CG3, CG4, and CG5 generate and distribute five programmable clock signals labeled CLK1, CLK2, CLK3, CLK4, and CLK5, respectively. In one embodiment, the five clock generators CG1 through CG5 are five identical circuits located within the synchronous dynamic random-access-memory (SDRAM) clocks module of an application specific integrated circuit (ASIC) controller. In alternate embodiments, CG1 through CG5 may be non-identical circuits.
Each clock generator preferably includes two clock signal input terminals, AIN and BIN. Each clock generator includes a clock signal output terminal COUT. In one embodiment, the AIN input terminals are all tied to a common dynamic-random-access-memory (DRAM) clock labeled DCLK. In one embodiment, DCLK is generated by a clock generator external to the controller. In alternate embodiments, DCLK may be generated within the ASIC controller.
The BIN input terminals are intended for use with a clock signal which has been externally looped-back. In one embodiment, the BIN input terminals of CG1 and CG2 are connected to the loopback connection""s pad, bond-wire, and lead of the ASIC. The BIN input terminals of CG3, CG4, and CG5 are not used, and therefore are tied to logic high (Vcc). Should it be determined that the BIN input terminals of CG1 and CG2 will not be used in a particular application, the loopback connection""s pad, bond-wire, and lead may be tied to a logic high that is external to the ASIC controller.
In one embodiment, the ASIC utilizes a control bus, and the memory controller of the ASIC includes a control bus interface. A signal line provides the contents of programmable registers within the control bus interface to each of the clock generators CG1, CG2, CG3, CG4, and CG5.
The clock signal output terminals COUT on the five programmable clock generators CG1, CG2, CG3, CG4, and CG5 are connected to various clock distribution signal lines. The clock signal output terminal COUT of CG1 is connected to the CLK1 distribution signal line. The CLK1 distribution signal line sends CLK1 to the clock input terminal of the first-stage pipeline data input flip-flop. The clock signal output terminal COUT of CG2 is connected to the CLK2 distribution signal line. The CLK2 distribution signal line sends CLK2 to the clock input terminal of the second-stage pipeline data input flip-flop. The clock signal output terminal COUT of CG3 is connected to the CLK3 distribution signal line. The CLK3 distribution signal line sends CLK3 to the SDRAM interface. The clock signal output terminal COUT of CG4 is connected to the CLK4 distribution signal line. The CLK4 distribution signal line sends CLK4 off the die of the ASIC controller via a pad, bond-wire, and lead. CLK4 is intended for use by the external SDRAM, and may also be looped-back to CG1 and CG2 via loopback pad, bond-wire, and lead. The clock signal output terminal COUT of CG5 is connected to the CLK5 distribution signal line. The CLK5 distribution signal line sends CLK5 to the clock input terminals of the data output flip-flop, the auxiliary data output flip-flop, the address output flip-flop, the row-address asserted strobe (RAS) and column-address asserted strobe (CAS) flip-flop, and the SDRAM control signals flip-flop.
The two clock signal input terminals, AIN and BIN, of each clock generator, CG1 through CG5, may be attached to a chain of digital buffer elements. At designated places in these chains, signal taps may be taken. The signals at these signal taps are clock signals delayed by amounts equal to the sum of the individual delays of the digital buffer elements prior to the signal tap. Any of the signals at the various signal taps may be selected for use as a delayed clock signal. The selection may be under software control by utilizing a selection mulitiplexor driven by the programmable register in the control bus interface. Thus, because the selection of clock delays is under software control, the delays may be programmed into the circuits after fabrication, and the delays may be tailored to a particular application of the circuits.